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HM5216165 Series
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Description Features
* * * * * * * * * * * *
16 M LVTTL Interface SDRAM (512-kword x 16-bit x 2-bank) 100 MHz/83 MHz
E0167H10 (Ver. 1.0) (Previous ADE-203-280C (Z)) Jun. 12, 2001
All inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance.
3.3 V Power supply Clock frequency: 100 MHz/83 MHz LVTTL interface Single pulsed RAS 2 Banks can operates simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8/full page 2 variations of burst sequence Sequential (BL = 1/2/4/8/full page) Interleave (BL = 1/2/4/8) Programmable CAS latency: 1/2/3 Byte control by DQMU and DQML Refresh cycles: 4096 refresh cycles/64 ms 2 variations of refresh Auto refresh Self refresh
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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HM5216165 Series
Ordering Information
Type No. Frequency 100 MHz 83 MHz Package 400-mil 50-pin plastic TSOP II (TTP-50D)
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HM5216165TT-10H HM5216165TT-12
Pin Arrangement
HM5216165TT Series VCC 1 2 3 4 5 6 7 8 9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 (Top view) VSS I/O15 I/O14 VSSQ I/O13 I/O12 VCCQ I/O11 I/O10 VSSQ I/O9 I/O8 VCCQ NC DQMU CLK NC A9 A8 A7 A6 A5 A4 CKE
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I/O0 I/O1 VSSQ I/O2 I/O3 VCCQ I/O4 I/O5 VSSQ I/O6 I/O7 VCCQ WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC DQML 2
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10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Data Sheet E0167H10
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HM5216165 Series
Pin Description
Pin name Function Address input Row address Column address Data-input/output Chip select Row address strobe command Column address strobe command Write enable command Upper byte input/output mask Lower byte input/output mask Clock input Clock enable A0 to A10 A0 to A7 A11
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A0 to A11 I/O0 to I/O15 CS RAS CAS WE DQMU DQML CLK CKE VCC VSS VCCQ VSS Q NC
Bank select address
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Power for I/O pin Ground for I/O pin No connection
Power for internal circuit Ground for internal circuit
Data Sheet E0167H10
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HM5216165 Series
Block Diagram
Sense amplifier & I/O bus
Memory array Column decoder
Sense amplifier & I/O bus
Column decoder
Data Sheet E0167H10
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DQMU
DQML
CKE
RAS
CAS
CLK
WE
CS
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Input buffer
A0 - A11
A0 - A7
A0 - A11
Column address counter
Column address buffer
Row address buffer
Refresh counter
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Row decoder Bank 0 2048 row X 256 column X 16 bit Output buffer I/O0 - I/O15
Row decoder
Memory array
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Bank 1 2048 row X 256 column X 16 bit
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Control logic & timing generator
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HM5216165 Series
Pin Functions
CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A10 (input pins): Row address (AX0 to AX10) is determined by A0 to A10 level at the bank active command cycle CLK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A11 (BS) is precharged. A11 (input pin): A11 is a bank select signal (BS). The memory array of the HM5216165 is divided into bank 0 and bank 1, both which contain 2048 row x 256 column x 16 bits. If A11 is Low, bank 0 is selected, and if A11 is High, bank 1 is selected. CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock suspend modes. DQMU/DQML (input pins): DQMU controls upper byte and DQML controls lower byte input/output buffers. Read operation: If DQMU/DQML is High, the output buffer becomes High-Z. If the DQMU/DQML is Low, the output buffer becomes Low-Z. Write operation: If DQMU/DQML is High, the previous data is held (the new data is not written). If DQMU/DQML is Low, the data is written. I/O0 to I/O15 (I/O pins): Data is input to and output from these pins. These pins are the same as those of a conventional DRAM.
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VCC and VCC Q (power supply pins): 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer). VSS and V SS Q (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.)
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Data Sheet E0167H10
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HM5216165 Series
Command Operation
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Command Truth Table
Function Ignore command No operation Burst stop in full page Precharge select bank Precharge all bank Refresh Mode register set 6
The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins.
Symbol DESL NOP BST READ READ A WRIT WRIT A ACTV CKE n-1 n H H H H H H H H x x x x x x x x x x x CS H L L L L L L L L L L L RAS CAS WE x H H H H H H L L L L L x H H L L L L H H H L L x H L H H L L H L L H L A0 A11 A10 to A9 x x x V V V V V V x x V x x x L H L H V L H x V x x x V V V V V x x x V
Column address and read command Read with auto-precharge
Column address and write command Write with auto-precharge Row address strobe and bank act.
Note: H: VIH. L: VIL. x: V IH or VIL. V: Valid address input
Ignore command [DESL]: When this command is set (CS is High), the synchronous DRAM ignore command input at the clock. However, the internal status is held. No operation [NOP]: This command is not an execution command. However, the internal operations continue. Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page (256)), and is illegal otherwise. Full page burst continues until this command is input. When data input/output is completed for a full-page of data (256), it automatically returns to the start address, and input/output is performed repeatedly.
Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0 to AY7) and the bank select address (BS). After the read operation, the output buffer becomes High-Z. Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4, or 8. When the burst length is full-page (256), this command is illegal.
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PRE H PALL H REF/SELF H MRS V H
Data Sheet E0167H10
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HM5216165 Series
Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY7) and the bank select address (A11) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY7) and the bank select address (A11). Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4, or 8, or after a single write operation. When the burst length is full-page (256), this command is illegal. Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A11 (BS) and determines the row address (AX0 to AX10). When A11 is Low, bank 0 is activated. When A11 is High, bank 1 is activated. Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A11. If A11 is Low, bank 0 is selected. If A11 is High, bank 1 is selected. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to A11) at the mode register set cycle. For details, refer to the mode register configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. DQM Truth Table
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Function
Upper byte write enable/output enable Lower byte write enable/output enable Upper byte write inhibit/output disable Lower byte write inhibit/output disable Note: H: VIH. L: VIL. x: V IH or VIL. I DOD is needed.
The HM5216165 series can mask input/output data by means of DQMU and DQML. DQMU masks the upper byte and DQML masks the lower byte. During reading, the output buffer is set to Low-Z by setting DQMU/DQML to Low, enabling data output. On the other hand, when DQMU/DQML is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQMU/DQML to Low. When DQMU/DQML is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQMU/DQML. For details, refer to the DQM control section of the HM5216165 operating instructions.
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Symbol ENBU ENBL CKE n-1 H H H H MASKU MASKL
Data Sheet E0167H10
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n x x x x L x x
DQMU
DQML x L x H
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HM5216165 Series
CKE Truth Table
CKE n-1 H L L REF SELF H H H H SELFX L L L L CS H x x L L L H L H L H RAS x x x L L H x H x H x CAS x x x L L H x H x H x WE x x x H H H x H x H x
Current state Active Any
Function
n L L H H L L L H H H H
Address x x x x x x x x x x x
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Clock suspend Idle Idle Idle Self-refresh Power down 8
Clock suspend mode entry Clock suspend Clock suspend mode exit
Auto refresh command Self refresh entry Power down entry
Note: H: VIH. L: VIL. x: V IH or VIL.
Clock suspend mode entry: The synchronous DRAM enters clock suspend mode from active mode by setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as shown below. ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. READ suspend and READ A suspend: The data being output is held (and continues to be output). WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During clock suspend mode, keep the CKE to Low.
Clock suspend mode exit: The synchronous DRAM exits from clock suspend mode by setting CKE to High during the clock suspend state. IDLE: In this state, all banks are not selected, and completed precharge operation.
Auto refresh command [REF]: When this command is input from the IDLE state, the synchronous DRAM starts auto refresh operation. (The auto refresh is the same as the CBR refresh of conventional DRAMs.) During the auto refresh operation, refresh address and bank select address are generated inside the synchronous DRAM. For every auto refresh cycle, the internal address counter is updated. Accordingly, 4096 times are required to refresh the entire memory. Before executing the auto refresh command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed after auto refresh, no precharge command is required after auto refresh.
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Self refresh exit Power down exit
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Data Sheet E0167H10
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HM5216165 Series
Self refresh entry [SELF]: When this command is input during the IDLE state, the synchronous DRAM starts self refresh operation. After the execution of this command, self refresh continues while CKE is Low. Since self refresh is performed internally and automatically, external refresh operations are unnecessary.
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Function Truth Table
Current state Precharge CS H L L L L L L L L Idle H L L L L L L L L
Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit. Self refresh exit: When this command is executed during self refresh mode, the synchronous DRAM can exit from self refresh mode. After exiting from self refresh mode, the synchronous DRAM enters the IDLE state. Power down exit: When this command is executed at the power down mode, the synchronous DRAM can exit from power down mode. After exiting from power down mode, the synchronous DRAM enters the IDLE state.
The following table shows the operations that are performed when each command is issued in each mode of the synchronous DRAM.
RAS CAS WE x H H H H L L L L x H H H H L L L L x x
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H H H L L L H H L L x H H L L H H L L H L H L H L x H L H L H L H L
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Address x x x DESL NOP BST BA, CA, A10 BA, CA, A10 BA, RA x x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE ACTV BA, A10 MODE MRS DESL NOP BST ACTV MRS
Command
Operation Enter IDLE after t RP Enter IDLE after t RP NOP ILLEGAL
READ/READ A WRIT/WRIT A
Data Sheet E0167H10
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ILLEGAL ILLEGAL NOP PRE, PALL REF, SELF ILLEGAL ILLEGAL NOP READ/READ A WRIT/WRIT A
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NOP NOP ILLEGAL ILLEGAL Bank and row active NOP Refresh Mode register set
PRE, PALL REF, SELF
HM5216165 Series
Current state Row active CS H L L L L L L L L RAS CAS WE x H H x H H L L H H L L x x H L H L H L H L x Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA Command DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A Operation NOP NOP NOP Begin read Begin write Other bank active ILLEGAL on same bank*3 Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop on full page Continue burst read to CAS latency and new read Term burst read/start write Other bank active ILLEGAL on same bank*3 Term burst read and Precharge ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge
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Read H L L L L L L L L Read with auto-precharge H L L L L L L L L 10
H H L L L
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x H H H H H L H H L L L L x H H H H L L L L L L H L H H L H L H L L x H H L L H H L L x H L H L H L H L
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ACTV BA, A10 x MODE MRS x x x DESL NOP BST BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE ACTV MRS
PRE, PALL
REF, SELF
Data Sheet E0167H10
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ILLEGAL READ/READ A WRIT/WRIT A ILLEGAL ILLEGAL PRE, PALL REF, SELF ILLEGAL ILLEGAL ILLEGAL
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Other bank active ILLEGAL on same bank*3
HM5216165 Series
Current state Write CS H L L L L L L L L RAS CAS WE x H H x H H L L H H L L x x H L H L H L H L x Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x Command DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST Operation Continue burst to end Continue burst to end Burst stop on full page Term burst and new read Term burst and new write Other bank active ILLEGAL on same bank*3 Term burst write and precharge*2 ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL ILLEGAL Other bank active ILLEGAL on same bank*3 ILLEGAL ILLEGAL
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Write with auto-precharge H L L L L L L L L Refresh (auto refresh) H L L L L L L L L
H H L L L
Notes: 1. H: VIH. L: VIL. x: V IH or VIL. The other combinations are inhibit. 2. An interval of t DPL is required between the final valid data input and the precharge command. 3. If tRRD is not satisfied, this operation is illegal.
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L x H H H H L L L L x H H H H L L L L H H H L L L H L H H L H L H L x H H L L H H L L L x H L H L H L H L
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BA, CA, A10 BA, CA, A10 BA, RA ACTV BA, A10 x MODE x x x MRS DESL NOP BST BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE ACTV MRS
READ/READ A WRIT/WRIT A
PRE, PALL
REF, SELF
Data Sheet E0167H10
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ILLEGAL READ/READ A WRIT/WRIT A ILLEGAL ILLEGAL ILLEGAL PRE, PALL REF, SELF ILLEGAL ILLEGAL ILLEGAL
Enter IDLE after t RC Enter IDLE after t RC
Enter IDLE after t RC
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HM5216165 Series
From [PRECHARGE] To [DESL], [NOR] or [BST]: When these commands are executed, the synchronous DRAM enters the IDLE state after tRP has elapsed from the completion of precharge.
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From [IDLE] From [ROW ACTIVE] From [READ]
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To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto refresh or self refresh). To [MRS]: The synchronous DRAM enters the mode register set cycle.
To [DESL], [NOP] or [BST]: These commands result in no operation. To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands set the synchronous DRAM to precharge mode. (However, an interval of t RAS is required.)
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. A f t e r CAS latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters precharge mode.
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Data Sheet E0167H10
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HM5216165 Series
From [READ with AUTO PRECHARGE] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the synchronous DRAM then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command.
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From [WRITE] From [REFRESH]
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM then enters precharge mode.
From [WRITE with AUTO-PRECHARGE]
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the synchronous DRAM enters precharge mode. To [ACTV]: This command makes the other bank active. (However, an interval of tRC is required.) Attempting to make the currently active bank active results in an illegal command.
To [DESL], [NOP], [BST]: After an auto-refresh cycle (after tRC), the synchronous DRAM automatically enters the IDLE state.
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Data Sheet E0167H10
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HM5216165 Series
Simplified State Diagram
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WRITE SUSPEND WRITEA SUSPEND POWER APPLIED
SELF REFRESH SR ENTRY SR EXIT
MODE REGISTER SET
MRS IDLE
REFRESH
*1 AUTO REFRESH
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state.
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BST (on full page)
CKE CKE_ IDLE POWER DOWN
ACTIVE CLOCK SUSPEND
ACTIVE
CKE_
Automatic transition after completion of command. Transition resulting from command input.
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CKE ROW ACTIVE WRITE Write CKE_ CKE WRITE WRITE WITH AP READ READ WITH AP WRITE WRITE WITH AP CKE_ WRITEA CKE READ WITH AP WRITE WITH AP PRECHARGE PRECHARGE PRECHARGE POWER ON PRECHARGE PRECHARGE
BST (on full page)
READ Read CKE_ CKE READ WITH AP READ SUSPEND
READ
Data Sheet E0167H10
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CKE_ CKE READA
READA SUSPEND
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HM5216165 Series
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A11) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A11, A10, A9, A8: (OPCODE): The synchronous DRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. Burst read and BURST WRITE: Burst write is performed for the specified burst length starting from the column address specified in the write cycle. Burst read and SINGLE WRITE: Data is only written to the column address specified during the write cycle, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. A6, A5, A4: (LMODE): These pins specify the CAS latency. A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected. A2, A1, A0: (BL): These pins specify the burst length.
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A11 A10 A9 OPCODE A11 A10 0 X X X 0 X X X A9 0 0 1 1 A8 0 1 0 1
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A8 A7 0 0 0 0 0 1 0 0 1 1 X Write mode R R
A6 A5 A4 CAS Latency 0 1 0 1 X R 1 2 3
Burst read and burst write Burst read and SINGLE WRITE
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A6 A5 A4 A3 A2 LMODE BT 1 R
A1 BL
A0
Data Sheet E0167H10
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A3 Burst Type 0 Sequential Interleave 0 0 0 0 1 1 1 0 0 1 1 0 1 1 1 0
A2 A1 A0 0 1 0 1 0 1 0 1
Burst Length BT=0 1 2 4 8 R R R BT=1 1 2 4 8 R R R R
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F.P. F.P. =Full Page (256) R is Reserved(inhibit) X: 0 or 1
HM5216165 Series
Burst Sequence
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A0 0 1 Starting Ad. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 16
Burst length = 2 Sequence 0, 1, 1, 0, Interleave 0, 1, 1, 0,
Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, A0 0 1 0 1 Sequence 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0,
Starting Ad. Addressing(decimal)
Burst length = 8
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A0 Sequence 0 1 0 1 0 1 0 1
0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4,
6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6,
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Data Sheet E0167H10
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HM5216165 Series
Operation of HM5216165 Series
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Read/Write Operations CAS Latency
CLK Command
ACTV
Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Either bank 0 or bank 1 is activated according to the status of the A11 pin, and the row address (AX0 to AX10) is activated by the A0 to A10 pins at the bank active command cycle. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CAS Latency-1) cycle after read command set. HM5216165 series can perform a burst read operation. The burst length can be set to 1, 2, 4, 8 or full-page (256). The start address for a burst read is specified by the column address (AY0 to AY7) and the bank select address (A11) at the read command set cycle. In a read operation, data output starts after the number of cycles specified by the CAS Latency. The CAS Latency can be set to 1, 2, 3. When the burst length is 1, 2, 4, or 8, the Dout buffer automatically becomes High-Z at the next cycle after the successive burst-length data has been output. When the burst length is full-page (256), data is repeatedly output until the burst stop command is input. The CAS latency and burst length must be specified at the mode register.
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t RCD
READ Row Column
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out 0 out 1 out 0 out 2 out 3 out 1 out 2 out 0 out 1
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out 3 out 2 out 3
Address
CL = 1 Dout CL = 2 CL = 3
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CL: CAS latency Burst length = 4
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Data Sheet E0167H10
HM5216165 Series
Burst Length
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CLK
t RCD
Command Address
ACTV
READ
Row
Column
BL = 1 BL = 2 BL = 4 BL = 8
out 0 out 0 out 1 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
out 255
Dout
BL = full page (256)
Write operation: Burst write or single write mode is selected by the OPCODE (A11, A10, A9, A8) of the mode register.
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t RCD
ACTV
WRIT
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
out 0
out 1
BL: Burst length CAS latency = 2
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in 1 in 1 in 1 in 1
in 2 in 2 in 2
Burst write
A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column address (AY0 to AY7) and the bank select address (A11) at the write command set cycle.
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in 5 in 5 in 6 in 6 in 7 in 7 in 8
CLK Command Address
Row
Column
BL = 1 BL = 2
in 0 in 0
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in 255
Din
in 0
in 3 in 3 in 3 in 4 in 4
BL = 4
in 0
BL = 8
in 0
in 0
in 1
BL = full page (256)
CAS latency = 1, 2, 3
Data Sheet E0167H10
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HM5216165 Series
Single write A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is only written to the column address (AY0 to AY7) and the bank select address (A11) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0).
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CLK Command Address Din
t RCD
Active Write
Row
Column
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in 0 CAS latency = 1, 2, 3 Burst length = 1, 2, 4, 8, full page
Pr
Data Sheet E0167H10
19
od t uc
HM5216165 Series
Auto Precharge Read with auto precharge: In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by l APR is required before execution of the next command.
CAS latency 3 2 1 Precharge start cycle 2 cycle before the final data is output 1 cycle before the final data is output same cycle as the final data is output
EO
CLK CL = 1 Command Dout CL = 2 Command Dout CL = 3 Command Dout
READ
L
READ
ACTV
Pr
out0 out1 out2 out3
lAPR
READ
ACTV
out0
out1
out2
out3 lAPR ACTV
out0
Note: Internal auto-precharge starts at the timing indicated by "
At CLK = 50 MHz ( lAPR changes depending on the operating frequency. )
Data Sheet E0167H10
20
od
out1 out2 out3 lAPR
".
t uc
HM5216165 Series
Write with auto precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval of lAPW is required between the final valid data input and input of the next command. Burst Write (Burst Length = 4)
EO
CLK Command WRIT I/O (input) in0
ACTV
L
in1 in2
WRIT in lAPW
in3 lAPW
Single Write
Pr
ACTV
CLK
Command
I/O (input)
od
1 2 3
Full-page Burst Stop
Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. The timing from command input to the last data changes depending on the CAS latency setting. In addition, the BST command is valid only during full-page burst mode, and is invalid with burst lengths 1, 2, 4 and 8.
CAS latency 1 2 3 BST to valid data 0 1 2 BST to high impedance
t uc
21
Data Sheet E0167H10
HM5216165 Series
CAS Latency = 1, Burst Length = full page
EO
CLK Command I/O (output)
out
BST
out
out
out
out
l BSR 0 cycle
l BSH 1 cycle
CAS Latency = 2, Burst Length = full page
L
out out
out out
CLK
Pr
out out out
out out out
Command I/O (output)
BST
out
l BSH = 2 cycle
l BSR = 1 cycle
od
BST
CAS Latency = 3, Burst Length = full page
CLK
Command
t uc
out out l BSH = 3 cycle
I/O (output)
l BSR = 2 cycle
Data Sheet E0167H10
22
HM5216165 Series
Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same cycle as the BST command and in subsequent cycles. In addition, the BST command is only valid during full-page burst mode, and is invalid with burst lengths of 1, 2, 4 and 8. And an interval of tDPL is required between the BST command and the next precharge command. Burst Length = full page
EO
CLK Command I/O (input)
BST
PRE/PALL
L
in in
t DPL I BSW = 0 cycle
Pr
Data Sheet E0167H10
23
od t uc
HM5216165 Series
Command Intervals Read command to Read command interval: Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cycle. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (same ROW address in same bank)
EO
CLK Command
Address (A0-A10)
BS (A11)
ACTV Row
L
READ READ Column A Column B
Pr
READ READ
Column A Column B
Dout
Bank0 Active
out A0 out B0 out B1 out B2 out B3
Column =A Column =B Column =A Column =B Dout Read Read Dout
CAS Latency = 3 Burst Length = 4 Bank0
Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (different bank)
od
out A0 out B0 out B1 out B2 out B3 Bank0 Bank1 Dout Dout
t uc
CAS Latency = 3 Burst Length = 4
CLK Command
Address (A0-A10)
BS (A11)
ACTV ACTV
Row 0
Row 1
Dout
Bank0 Active Bank1 Bank0 Bank1 Active Read Read
Data Sheet E0167H10
24
HM5216165 Series
Write command to Write command interval: Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 cycle. In the case of burst writes, the second write command has priority. WRITE to WRITE Command Interval (same ROW address in same bank)
EO
CLK Command
Address (A0-A10)
ACTV
Row
WRIT
WRIT
L
Column A Column B
BS (A11)
Din
in A0
in B0
in B1
in B2
in B3
Bank0 Active
Column =A Column =B Write Write
Burst Write Mode Burst Length = 4 Bank0
Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. In the case of burst write, the second write command has priority. WRITE to WRITE Command Interval (different bank)
Pr
WRIT
Column A Column B
od
in B2 in B3
CLK Command
Address (A0-A10)
BS (A11)
ACTV ACTV WRIT
t uc
Burst Write Mode Burst Length = 4
Row 0
Row 1
Din
Bank0 Active
in A0
in B0
in B1
Bank1 Bank0 Bank1 Active Write Write
Data Sheet E0167H10
25
HM5216165 Series
Read command to Write command interval: Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 cycle. However, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. READ to WRITE Command Interval (1)
EO
CLK Command
CL=1
DQMU /DQML
READ WRIT
Din
Dout
READ to WRITE Command Interval (2)
Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command.
Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input.
L
CL=2 CL=3
Pr
in B0 in B1 in B2 in B3 High-Z READ WRIT
Burst Length = 4 Burst write
CLK Command
od
2 clock
DQMU /DQML
CL=1
High-Z
Dout CL=2
CL=3
High-Z
High-Z
t uc
Din
Data Sheet E0167H10
26
HM5216165 Series
Write command to Read command interval: Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 cycle. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. WRITE to READ Command Interval (1)
EO
CLK Command DQMU/DQML Din Dout
CLK Command DQMU/DQML Din Dout
WRIT
READ
WRITE to READ Command Interval (2)
Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-active command. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed (as in the case of the same bank and the same address).
L
in A0 out B0 Column=A Write CAS Latency out B1 out B2 out B3
WRIT
in A0
Column=A Write
Pr
Column=B Read Column=B Dout
Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank0
od
out B0 out B1 out B2 out B3
READ
in A1
t uc
Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank0
CAS Latency Column=B Read Column=B Dout
Data Sheet E0167H10
27
HM5216165 Series
Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by lHZP, there is a possibility that burst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the cycles defined by lEP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (same bank): To output all data CAS Latency = 1, Burst Length = 4
EO
CLK Command Dout CLK Command Dout CLK Command Dout
CAS Latency = 2, Burst Length = 4
CAS Latency = 3, Burst Length = 4
L
READ CL=1 READ CL=2 READ
PRE/PALL
out A0
out A1
out A2
out A3
l EP = 0 cycle
Pr
PRE/PALL
od
out A1 out A2 out A3 l EP = -1 cycle
out A0
t uc
out A3
PRE/PALL
out A0
out A1
out A2
CL=3
l EP = -2 cycle
Data Sheet E0167H10
28
HM5216165 Series
READ to PRECHARGE Command Interval (same bank): To stop output data CAS Latency = 1, Burst Length = 1, 2, 4, 8
EO
CLK Command Dout CLK Command Dout CLK Command Dout
READ
PRE/PALL
High-Z out A0
l HZP =1
CAS Latency = 2, Burst Length = 1, 2, 4, 8
CAS Latency = 3, Burst Length = 1, 2, 4, 8
L
READ
PRE/PALL
Pr
High-Z out A0 l HZP =2
od
High-Z out A0
READ
PRE/PALL
l HZP =3
t uc
Data Sheet E0167H10
29
HM5216165 Series
Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cycle.
EO
CLK Command DQM Din
WRITE to PRECHARGE Command Interval (same bank): However, if the burst write operation is unfinished, the input data must be masked by means of DQMU and DQML for assurance of the cycle defined by tDPL.
WRITE to PRECHARGE Command Interval (same bank) Burst Length = 4 (To stop write operation)
L
WRIT
PRE/PALL
Pr
PRE/PALL
t DPL
CLK
Command
WRIT
od t uc
PRE/PALL
in A3 t DPL
DQM
Din
in A0
in A1
t DPL
Burst Length = 4 (To write all data)
CLK
Command
WRIT
DQM
Din
in A0
in A1
in A2
Data Sheet E0167H10
30
HM5216165 Series
Bank active command interval: Same bank: The interval between the two bank-active commands must be no less than tRC.
EO
CLK Command ACTV Address (A0-A10) BS (A11) ROW Bank 0 Active
In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. Bank active to bank active for same bank
ACTV
Bank active to bank active for different bank
L
t RC
ROW
Pr od
ACTV ROW:1 ACTV ROW:0 t RRD Bank 0 Active Bank 1 Active
Bank 0 Active
CLK
Command Address (A0-A10)
BS (A11)
t uc
31
Data Sheet E0167H10
HM5216165 Series
Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than tRSA .
EO
CLK Command Address (A0-A11) 32
MRS
ACTV
CODE
BS & ROW
L
t RSA Bank Active
Mode Register Set
Pr
Data Sheet E0167H10
od t uc
HM5216165 Series
DQM Control The DQMU and DQML mask the lower and upper bytes of the I/O data, respectively. The timing of DQMU/DQML is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQMU/DQML. By setting DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQMU/DQML during reading is 2.
I/O (input)
; ;;
DQMU /DQML in 0 in 1 in 3 l DID = 0 Latency
EO
CLK DQMU /DQML I/O (output) CLK
Writing: Input data can be masked by DQMU/DQML. By setting DQMU/DQML to Low, data can be written. In addition, when DQMU/DQML is set to High, the corresponding data is not written, and the previous data is held. The latency of DQMU/DQML during writing is 0.
L
High-Z out 0 out 1 out 3
Pr
lDOD = 2 Latency
Data Sheet E0167H10
33
od
t uc
HM5216165 Series
Refresh Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the autorefresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4096 cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer becomes HighZ after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A selfrefresh is terminated by a self-refresh exit command. If you use distributed auto-refresh mode with 15.6 s interval in normal read/write cycle, auto-refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. If you use address refresh or burst auto-refresh mode in normal read/write cycle, 4096 cycles of distributed auto-refresh with 15.6 s interval should be executed within 64 ms immediately after exiting from and before entering into self refresh mode.
EO
Others
34
Power-down mode: The synchronous DRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the synchronous DRAM exits from the power down mode, and command input is enabled from the next cycle. In this mode, internal refresh is not performed. Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the synchronous DRAM enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the synchronous DRAM terminates clock suspend mode, and command input is enabled from the next cycle. For details, refer to the "CKE Truth Table". Power-up sequence: During power-up sequence, the DQMU/DQML and the CKE must be set to High. When 200 s has past after power on, all banks must be precharged using the precharge command. After tRP delay, set 8 or more auto refresh commands. And set the mode register set command to initialize the mode register.
L
Pr
Data Sheet E0167H10
od
t uc
HM5216165 Series
Absolute Maximum Ratings
Parameter Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +4.6 -1.0 to +4.6 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Note 1 1
EO
Power dissipation Operating temperature Storage temperature Note: Parameter Supply voltage Input high voltage Input low voltage
Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current
1. Respect to V SS
Recommended DC Operating Conditions (Ta = 0 to +70C)
Symbol VCC, VCCQ VSS , VSS Q VIH Min 3.0 0 Max 3.6 0 4.6 0.8 Unit V V V V 1, 2 1, 3 Notes 1
Notes: 1. All voltage referred to VSS 2. VIH (max) = 5.5 V for pulse width 5 ns 3. VIL (min) = -1.0 V for pulse width 5 ns
L
Pr
2.0 VIL -0.3
Data Sheet E0167H10
35
od t uc
HM5216165 Series
DC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V)
HM5216165 -10H Symbol I CC1 I CC2 Min -- Max 130 -12 Min -- Max 105 Unit mA Test conditions Burst length = 1 t RC = min -- -- 3 2 -- -- 3 2 mA mA CKE = VIL, t CK = min 5 CKE = VIL CLK = VIL or VIH Fixed CKE = VIH, NOP command t CK = min 6 Notes 1, 2, 4
EO
Parameter Operating current Standby current (Bank Disable) Active standby current (Bank active) Burst operating current (CAS latency = 1) (CAS latency = 2) (CAS latency = 3) Refresh current Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage 36
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signal transition is once per two CLK cycles. 4. Input signal transition is once per one CLK cycle. 5. After power down mode, CLK operating current. 6. After power down mode, no CLK operating current. 7. After self refresh mode set, self refresh current.
L
I CC3 I CC4 I CC4 I CC4 I CC5 I CC6 I LI I LO VOH VOL
--
50
--
41
mA
3
-- --
7 51
-- --
7 43
mA mA
CKE = VIL, t CK = min, 1, 2 I/O = High-Z CKE = VIH, NOP command t CK = min, I/O = High-Z t CK = min, BL = 4 1, 2, 3
Pr
-- -- -- -- -- -10 -10 2.4 -- 65 -- -- -- -- -- 55 85 100 150 85 2 125 70 2 10 10 -- -10 -10 10 10 2.4 -- -- 0.4 0.4
mA mA mA
1, 2, 4
Data Sheet E0167H10
od
mA t RC = min mA A A V V
VIH VCC - 0.2 VIL 0.2 V 0 Vin VCC 0 Vout VCC I/O = disable
7
I OH = -2 mA I OL = 2 mA
t uc
HM5216165 Series
Capacitance (Ta = 25C, VCC, VCCQ = 3.3 V 0.3 V)
Parameter Symbol CI1 CI2 CO Min 2 2 4 Max 5 5 7 Unit pF pF pF Notes 1, 3 1, 3 1, 2, 3
EO
Output capacitance (I/O) Parameter System clock cycle time (CAS latency = 1) (CAS latency = 2) (CAS latency = 3) CLK high pulse width CLK low pulse width Access time from CLK (CAS latency = 1) (CAS latency = 2) (CAS latency = 3) Data-out hold time (CAS latency = 2, 3) Data-in setup time Data in hold time Address setup time Address hold time CKE setup time CKE hold time
Input capacitance (Address) Input capacitance (Signals)
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQMU/DQML = VIH to disable Dout. 3. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V)
CLK to Data-out low impedance CLK to Data-out high impedance (CAS latency = 1)
CKE setup time for power down exit
L
HM5216165 -10H Symbol t CK t CK t CK Min 30 15 10 3 3 Max -- -- -- -- -- -12 Min 36 18 12 4 4 -- -- -- 3 0 Max -- -- -- -- -- 32 12 9 ns ns ns 1 1 1, 2 Unit ns Notes 1
Pr
t CKH t CKL t AC t AC t AC t OH t LZ t HZ t HZ t DS t DH t AS t AH t CES t CESP t CEH -- -- -- 3 0 27 9 7.5 -- -- -- -- 2 1 2 1 2 2 1 13 7 -- -- -- -- -- -- --
Data Sheet E0167H10
37
od
-- -- -- -- 3 1 3 1 3 3 1 15 9 -- -- -- -- -- -- --
ns ns ns
1, 2 1, 2, 3 1, 4
t uc
ns ns ns ns ns ns ns 1 1 1 1 1, 5 1 1
HM5216165 Series
AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) (cont)
HM5216165 -10H Symbol t CS t CH t RC t RAS t RASC t RCD t RP Min 2 1 90 60 -- 30 30 15 20 1 Max -- -- -- -12 Min 3 1 100 Max -- -- -- Unit ns ns ns Notes 1 1 1 1 1 1 1 1 1
EO
Parameter Refresh period Notes: 1. 2. 3. 4. 5.
Command (CS, RAS, CAS, WE, DQM) setup time Command (CS, RAS, CAS, WE, DQM) hold time Ref/Active to Ref/Active command period Active to precharge command period Active to precharge on full page mode Active command to column command (same bank) Precharge to active command period
120000 70 120000 -- -- -- -- -- 5 30 30 15 20 1 --
120000 ns 120000 ns -- -- -- -- 5 64 ns ns ns ns ns ms
Write recovery or data-in to precharge lead t DPL time Active (a) to Active (b) command period Transition time (rise to fall)
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.40 V. Access time is measured at 1.40 V. Load condition is CL = 50 pF with current source. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CKE rising edge except power down exit command.
Test Conditions
* Input and output timing reference levels: 1.4 V * Input waveform and output load: See following figures
2.8 V
L
t
T
Pr
t RRD tT t REF -- 64 80% 20% tT
od
Output I/O CL
t uc
500 +1.4 V
Input
V SS
Data Sheet E0167H10
38
HM5216165 Series
Relationship Between Frequency and Minimum Latency
HM5216165 -10H Symbol t RCD t RC 100 10 3 9 6 3 2 2 2 5 9 3 66 15 2 6 4 2 1 2 2 3 6 3 2 33 30 1 3 2 1 1 1 2 2 3 3 2 -12 83 12 3 9 6 3 2 2 2 5 9 3 -- -- 55 18 2 6 4 2 1 2 2 3 6 3 2 28 36 1 3 2 1 1 1 2 2 3 3 2 1 1 Notes 1 = [tRAS + tRP] 1 1 1 1 1 2 = [tDPL + tRP] = [tRC]
EO
Parameter Frequency (MHz) tCK (ns) Self refresh exit time (CAS latency = 2) (CAS latency = 1) (CAS latency = 2) (CAS latency = 1) DQM to data in DQM to data out CKE to CLK disable
Active command to column command (same bank) Active command to active command (same bank)
Active command to precharge command t RAS (same bank) Precharge command to active command t RP (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) t DPL t RRD I SREX
Last data in to active command (Auto precharge, same bank)
Self refresh exit to command input
Precharge command to high impedance (CAS latency = 3) I HZP I HZP I HZP
Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) (CAS latency = 3)
Column command to column command I CCD Write command to data in latency I WCD I DID I DOD I CLE
L
Pr
I APW I SEC -- -- 1 -- 1 I APR I EP I EP I EP -2 -- -- 1 0 0 2 1 -2 -1 -- 1 0 0 2 1
Data Sheet E0167H10
39
od
1 -- 1 1 1 -2 -2 -2 -1 0 1 0 0 2 1 -- -1 -- -- 1 0 0 2 1 1 0 0 2 1
-2 -1
t uc
0 1 0 0 2 1
HM5216165 Series
Relationship Between Frequency and Minimum Latency (cont)
HM5216165 -10H Symbol t RSA I CDD I PEC I BSR I BSR I BSR I BSH I BSH I BSH 100 10 1 0 1 2 -- -- 3 -- -- 0 66 15 1 0 1 2 1 -- 3 2 -- 0 33 30 1 0 1 2 1 0 3 2 1 -12 83 12 1 0 1 2 -- -- 3 -- -- 0 55 18 1 0 1 2 1 -- 3 2 -- 0 28 36 1 0 1 2 1 0 3 2 1 0 Notes
EO
Parameter Frequency (MHz) tCK (ns) CS to command disable (CAS latency = 2) (CAS latency = 1) (CAS latency = 2) (CAS latency = 1) 40
Register set to active command
Power down exit to command input Burst stop to output valid data hold (CAS latency = 3)
Burst stop to output high impedance (CAS latency = 3)
Burst stop to write data ignore
Notes: 1. t RCD to tRRD are recommended value. 2. When self refresh exit is executed, CKE should be kept "H" longer than l SREX from exit cycle.
L
Pr
I BSW
0
Data Sheet E0167H10
od t uc
HM5216165 Series
Timing Waveforms
; ;; ;;; ; ;; ;; ;
t CK t CKH t CKL
; ;;;; ;; ; ;;;; ;
t CS t CH t CS t CH t CS t CH t CS t CH
EO
Read Cycle
CLK
VIH
t RC
CKE
t RCD
t RAS
t RP
CS
t CS t CH
t CS t CH
L
t CS t CH t CS t CH t CS t CH t CS t CH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t CS Bank 0 Active Bank 0 Read
t CS t CH
t CS t CH
RAS
t CS t CH
t CS t CH
CAS
t CS t CH
t CS t CH
Pr
t AS t AH t AS t AH t CH t AC t AC t AC t AC t LZ t OH t OH t OH Bank 0 Precharge
WE
t AS t AH t AS t AH
A11
A10
t AS t AH
Address
od
t HZ
DQMU /DQML
I/O(input)
I/O(output)
Burst length = 4 Bank0 Access = VIH or VIL
t uc
41
Data Sheet E0167H10
;; ;; ;; ;;;; ;
HM5216165 Series
Write Cycle
t CK
;;; ; ;;
CS
t CS t CH t CS t CH t CS t CH t CS t CH
EO
CLK
VIH
t CKH t CKL
t RC
CKE
t RCD
t RAS
t RP
t CS t CH
t CS t CH
t CS t CH
t CS t CH
RAS
t CS t CH
t CS t CH
t CS t CH
t CS t CH
L
t CS t CH t CS t CH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t CS Bank 0 Active Bank 0 Write
CAS
t CS t CH
t CS t CH
WE
t AS t AH
t AS t AH t AS t AH
A11
Pr
t CH t DS t DH tDS t DH t DS t DH t DS t DH t RWL
t AS t AH
A10
t AS t AH
Address
DQMU /DQML
od
Bank 0 Precharge
I/O(input)
I/O(output)
Burst length = 4 Bank0 Access = VIH or VIL
t uc
Data Sheet E0167H10
42
HM5216165 Series
Mode Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
;;; ;;;; ;; ;;; ;; ;; ; ;;;; ;;;;; ; ;; ;
EO
CLK CKE CS
VIH
RAS
CAS
WE
;
A11(BS)
L
valid t RP t RSA
Precharge If needed
Address
code R: b
C: b
C: b'
DQMU /DQML I/O(output) I/O(input)
b
b+3
b'
b'+1
b'+2
b'+3
High-Z
t RCD
Output mask
Mode Bank 1 register Active Set
Bank 1 Read
tRCD = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL
Pr
Data Sheet E0167H10
od t uc
43
;; ;;;; ;; ;; ; ;;;; ;;; ; ;; ;
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
;;
HM5216165 Series
Read Cycle/Write Cycle
EO
CLK CS CKE
VIH
RAS CAS
Read cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL
WE
A11(BS)
Address DQMU /DQML I/O (output) I/O (input) CKE CS
R:a
C:a
R:b
C:b
C:b'
C:b"
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
Bank 1 Read
b'+1 b"
b"+1 b"+2 b"+3
High-Z
Bank 0 Active
Bank 0 Read
Bank 1 Active
Bank 1 Bank 0 Read Precharge
Bank 1 Read
Bank 1 Precharge
VIH
L
R:a C:a R:b a a+1 a+2 a+3
Bank 1 Active Bank 0 Write
RAS CAS
Write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL
WE
Pr
C:b C:b'
High-Z
A11(BS)
Address DQMU /DQML I/O (output) I/O (input)
C:b"
b
b+1 b+2 b+3 b'
Bank 0 Precharge
b'+1 b"
b"+1 b"+2 b"+3
Bank 0 Active
Bank 1 Write
Bank 1 Write
Bank 1 Write
Bank 1 Precharge
Data Sheet E0167H10
44
od
t uc
HM5216165 Series
Read/Single Write Cycle
0 1
;
a b c a a+1 a+3
;; ;; ;; ;; ;;; ; ;; ; ;; ;; ; ;;;;
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
EO
CLK CS CKE
VIH
RAS CAS
WE
A11(BS)
Address DQMU /DQML I/O (input) I/O (output) CKE CS
R:a
C:a
R:b
C:a' C:a a
VIH
L
Bank 0 Active Bank 0 Read
a
a+1 a+2 a+3
a
a+1 a+2 a+3
Bank 0 Precharge
Bank 1 Active
Bank 0 Bank 0 Write Read
Bank 1 Precharge
RAS CAS
Pr
R:b C:a
Bank 1 Active Bank 0 Write
WE
A11(BS)
Address DQMU /DQML I/O (input) I/O (output)
R:a
C:a
C:b C:c
od
Bank 0 Bank 0 Write Write
Bank 0 Active
Bank 0 Read
Bank 0 Precharge
Read/Single write RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL
t uc
45
Data Sheet E0167H10
HM5216165 Series
Read/Burst Write Cycle
0 1
;
a b c a a+1 a+3
;; ;; ;; ;; ;;; ; ;; ; ;; ;; ; ;;;;
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
EO
CLK CS CKE
VIH
RAS CAS
WE
A11(BS)
Address DQMU /DQML I/O (input) I/O (output) CKE CS
R:a
C:a
R:b
C:a' C:a a
VIH
L
Bank 0 Active Bank 0 Read
a
a+1 a+2 a+3
a
a+1 a+2 a+3
Bank 0 Precharge
Bank 1 Active
Bank 0 Bank 0 Write Read
Bank 1 Precharge
RAS CAS
Pr
R:b C:a
Bank 1 Active Bank 0 Write
WE
A11(BS)
Address DQMU /DQML I/O (input) I/O (output)
R:a
C:a
C:b C:c
od
Bank 0 Bank 0 Write Write
Bank 0 Active
Bank 0 Read
Bank 0 Precharge
Read/Single write RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL
t uc
Data Sheet E0167H10
46
;;; ; ;;; ;; ;
HM5216165 Series
Full Page Read/Write Cycle
0 1 2 3 4 5 6 7 8 9 260 261 262 263 264 265 266 267 268 269
EO
CLK CS CKE
VIH
RAS CAS
Read cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page = VIH or VIL
WE
A11(BS) Address DQMU /DQML I/O (output) I/O (input) CKE CS
R:a
C:a
R:b
a
a+1
a+2
a+3
a-2
a-1
a
a+1
a+2
a+3
a+4
a+5
High-Z
Bank 0 Active
Bank 0 Read
Bank 1 Active
Burst stop
Bank 1 Precharge
L
R:a C:a R:b a a+1 a+2 a+3 Bank 0 Write Bank 1 Active
VIH
RAS CAS
Write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page = VIH or VIL
WE
A11(BS)
Pr
High-Z
a+4 a+5
a+6
Address DQMU /DQML I/O (output) I/O (input)
a+1
a+2
a+3
a+4
a+5
Bank 0 Active
Burst stop
Bank 1 Precharge
Data Sheet E0167H10
od
t uc
47
HM5216165 Series
Auto Refresh Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
;
CLK ISREX CKE CS
CKE Low CKE High
;; ;;;;; ; ;;; ; ;; ;;;;; ;;; ;;;;; ;; ; ; ;
EO
CLK CKE CS
VIH
RAS
CAS WE
A11(BS)
Address
A10=1
R:a
C:a
DQMU /DQML I/O(input)
L
t RP
Precharge If needed Auto Refresh
A10=1
I/O(output)
High-Z
a
a+1
t RC
tRC
Auto Refresh
Active Bank 0
Read Bank 0
Refresh cycle and Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL
Pr
High-Z Self refresh exit ignore command or No operation
Self Refresh Cycle
od
tRC
Next Self refresh entry clock command enable
RAS
CAS WE
A11(BS)
Address DQMU /DQML I/O(imput) I/O(output)
t uc
Next Auto clock refresh enable
tRP
Precharge command If needed Self refresh entry command
Self refresh cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 =VIH or VIL
Data Sheet E0167H10
48
HM5216165 Series
Clock Suspend Mode
t CESP t CEH t CES
;;;; ;; ;;;; ;; ;;;;;; ; ; ;;;; ;; ; ;;; ;; ;;;;
EO
0 1 2 CLK CS CKE RAS CAS WE A11(BS) Address DQMU /DQML I/O (output) I/O (input) CKE CS R:a
Bank0 Active clock Active suspend start
; ;
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL
C:a
R:b
C:b
a
a+1 a+2
a+3
b
b+1 b+2 b+3
L
R:a a
Active clock suspend start
High-Z
Active clock Bank0 suspend end Read
Bank1 Active
Read suspend start
Read suspend end
Bank1 Read
Bank0 Precharge
Earliest Bank1 Precharge
RAS CAS
Write cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL
Pr
C:a R:b C:b
High-Z
WE
A11(BS)
Address DQMU /DQML I/O (output) I/O (input)
a+1 a+2
a+3 b
b+1 b+2 b+3
Bank0 Active
Active clock Bank0 Bank1 supend end Write Active
Write suspend start
Write suspend end
Bank1 Bank0 Write Precharge
Earliest Bank1 Precharge
Data Sheet E0167H10
49
od
t uc
HM5216165 Series
Power Down Mode
;
Precharge command If needed Power down entry Power down mode exit Active Bank 0
;;;;; ;; ;;; ;;;;;; ;;;;;; ;;;; ;;;;; ;;;; ;;; ;; ; ;
EO
CLK CKE CS RAS CAS WE A11(BS) Address DQMU /DQML I/O(input) I/O(output)
CKE Low
Power Up Sequence
L
A10=1
R: a
Pr
High-Z
tRP
Power down cycle RAS-CAS delay=3 CAS latency=2 Burst length=4 = VIH or VIL
od
7 8 9 10 48 49 50 High-Z tRC Auto Refresh
0
1
2
3
4
5
6
51
52
53
54
55
CLK
CKE CS RAS CAS
VIH
t uc
code Valld
WE Address DQMU /DQML I/O tRP All banks Auto Refresh Precharge tRC
Valld
VIH
tRSA Mode register Bank active Set If needed
Data Sheet E0167H10
50
HM5216165 Series
Package Dimensions
HM5216165TT Series (TTP-50D)
Unit: mm
1
0.80
25 0.80
0.27 0.07 0.25 0.05 1.15 Max 1.20 Max
0.13 M 11.76 0.20
10.16
0.145 0.05 0.125 0.04
0.10
0.13 0.05
0.50 0.10
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TTP-50D -- -- 0.50 g
Data Sheet E0167H10
51
0.68
EO
50
20.95 21.35 Max 26
L
Pr
0 - 5
od
t uc

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